The present application relates to a semiconductor structure and a method of forming a semiconductor structure. More particularly, the present application relates to a method of forming a semiconductor nanowire laterally from a portion of a sidewall of a semiconductor pillar.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continued scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor nanowire field effect transistors is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. In its basic form, semiconductor nanowire field effect transistors include at least one semiconductor nanowire including a source region, a drain region and a channel region located between the source region and the drain region, and a gate electrode that is formed straddling over the channel region of the at least one semiconductor nanowire. A gate dielectric is typically disposed between the channel region of the at least one semiconductor nanowire and the gate electrode. The gate electrode regulates electron flow through the semiconductor nanowire channel between the source region and the drain region.
Semiconductor nanowire field effect transistors can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs. One problem associated with conventional semiconductor nanowire field effect transistors that include high mobility channel materials such as, a III-V compound semiconductor, is that the semiconductor nanowire that is grown typically has defects associated therewith which hinder the performance of the device.